Open Source Summit Japan & Automotive Linux Summit 2021

SOC designs have evolved continuously over the last decade and with more and more computing units, H/W accelerators being integrated into the system in order to upscale the performance, and the advent of device specific SMMU and caches, data sharing has become a relatively complex affair. On the contrary, it has also made data sharing faster, adding to performance. Maintaining data coherency across various devices and CPUs is one of the key prerequisites to extract maximum performance from complex data sharing systems. Having said that, we often do find components in an SOC which offer limited/no support from H/W side for coherency. A fool proof system should take care of such constraints and limitations in software. In this session, we cover the basics of caching and coherency problems which arise in modern SOCs, and an overview of how much support Linux offers for maintaining data coherency across devices in various ways. We take example of an ARM64 system and touch upon basic ARM SMMU hardware, basic AXI signals, their significance and how they participate in achieving coherency. We will also look into main APIs provided by Linux DMA-IOMMU layer to achieve the fool proof coherent system which manages both type of devices - the coherent and the non-coherent.