Open Source Summit Japan & Automotive Linux Summit 2021

PCIe is the industry standard I/O, serialized point-to-point interconnect protocol, which provides high-bandwidth scalable solution for reliable data transfer. PCIe architecture is designed to support future performance enhancements via speed upgrades and advance encoding techniques. However, the limitations of the SoC incorporating the PCIe controller hinders it from exhibiting its full potential. Factors such as Link width, Payload size, operating frequency of the SoC, Data path latency, TX/RX Buffer size etc. plays a crucial role in determining the performance of the PCIe system. SoC designers and SoC users need to deeply understand raw bit rate and various factors of PCIe technology which can impact performance. Fortunately, majority of PCIe H/W Controller designs provides S/W accessible tuning registers and performance enhancing features, thereby bringing down most of the hindrances specified earlier. Taking Synopsis DesignWare PCIe controller as example, this talk showcases some of the H/W configurations which can be tuned by the end user or system administrator using S/W utilities running in Userspace. This talk also highlights the visible performance improvements after tuning and the practicality of using tuning knobs on different PCIe based subsystems.