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Automotive System-on-Chip (SoC) has to meet stringent reliability standards to ensure functional safety mandated to achieve Automotive Safety Integrity Levels (ASIL) certification. As we move to the future technologies, SoC failures are observed due to shrinking silicon process nodes, impacting the functional safety. Being a primary communication interface in automotive SoCs, PCIe H/W designs need to be bulletproofed by implementing more advanced Reliability, Availability and Serviceability (RAS) mechanisms. This talk proposes a S/W framework to extract RAS information from the PCIe controller and allow developers and end-users to detect, recover and prevent potential hazards without using any expensive hardware based PCIe analyzers. The main advantage of this software based framework is that it can be used in chip to chip communication over PCIe, where PCIe lanes are routed inside PCB without having any test probes. The talk also demonstrates on how the developed software framework was utilized in detecting some of the hardware errors during SoC bring up. The proposed framework uses simple debugfs based interface to expose some of the powerful RAS features to user space. Implementation of the driver is under review in Linux mailing list @ https://lkml.org/lkml/2021/5/18/1371.
